1. Field of the Invention
This invention generally relates to class-D amplifiers used for power amplification of audio signals, and in particular to triangular wave generating circuits, which are used for converting analog audio signals into pulse signals.
This application claims priority on Japanese Patent Application No. 2004-197384, the content of which is incorporated herein by reference.
2. Description of the Related Art
It is conventionally known that class-D amplifiers have simplified circuit configurations, which are simplified in the scale of the power source circuitry without using stabilized power sources. Japanese Patent Application Publication No. 2004-7324 (corresponding to U.S. Pat. No. 6,791,405 B2) teaches a technology in which triangular waves used for conversion of analog audio signals into pulse signals are controlled so as to cause variations with respect to wave heights of triangular waves following variations of voltages, thus suppressing variations of amplification gains.
FIG. 4 is a circuit diagram showing a conventionally known triangular wave generating circuit, wherein reference numeral 21 designates a terminal for inputting a reference clock pulse signal CK. Reference numeral 22 designates a digital phase comparator, which compares the phase of the clock pulse signal CK supplied to a reference input terminal IN and the phase of a signal NFB supplied to a comparison input terminal REF, so that it outputs a high-level signal (or a signal ‘H’) from an output terminal UP or an output terminal DW. Reference numeral 23 designates a loop filter that converts an output signal of the phase comparator 22 into an analog signal PLLC. Reference numeral 24 designates a circuit including capacitors 25 and 26 and a resistor 27, wherein the circuit 24 and the loop filter 23 are combined together to form a low-pass filter, so that the circuit 24 removes high frequency components from the output signal of the loop filter 23.
Reference numeral 30 designates an operational amplifier in which a non-inverting input terminal receives the output signal PLLC of the loop filter 23, an inverting input terminal is connected to a source of a field-effect transistor (FET) 32, and an output terminal is connected to a gate of the FET 32. The source of the FET 32 is grounded via a resistor 31, and a drain of the FET 32 is connected to a negative power source (whose voltage is set to −5V) via a load circuit 33. The load circuit 33 serves as a load for the FET 32 and is constituted by a single field-effect transistor. The operational amplifier 30, FET 32 and resistor 31 form a circuit that controls an electric current flowing through the load circuit 33 in response to the level of the output signal PLLC of the loop filter 23.
Reference numerals 34 and 35 designate constant current circuits each having a current value that is controlled by an electric current flowing through the load circuit 33, whereby they allow electric currents identical to the electric current flowing through the load circuit 33 to flow therethrough. Reference numerals 36 and 37 designate switches that are controlled to be turned on and off in response to the signal NFB. That is, when the signal NFB is at a low level (‘L’), the switch 36 is turned on, but the switch 37 is turned off. When it is at a high level (‘H’), the switch 36 is turned off, but the switch 37 is turned on. Reference numeral 39 designates an operational amplifier in which a non-inverting input terminal is grounded, an inverting input terminal is connected to a connection point between the switches 36 and 37, and an output terminal is connected to an output terminal 46. Reference numeral 40 designates a capacitor that is connected between the non-inverting input terminal and inverting input terminal of the operational amplifier 39. The operational amplifier 39 and the capacitor 40 are combined together to form an integration circuit.
Reference numeral 41 designates a comparator whose inverting input terminal receives the output signal of the operational amplifier 39. A voltage that is produced by dividing a voltage VPX by means of resistors 81 and 82 is applied to a non-inverting input terminal of the comparator 41. Reference numeral 42 designates a comparator in which an inverting input terminal receives the output signal of the operational amplifier 39, and a voltage that is produced by dividing a voltage VMX by means of resistors 83 and 84 is applied to a non-inverting input terminal. Herein, both of the resistors 81 and 83 have the same resistance, and both of the resistors 82 and 84 have the same resistance.
The output of the comparator 41 is applied to a first input of a NAND gate 44, and the output of the comparator 42 is applied to a first input of a NAND gate 45 via an inverter 43. The NAND gates 44 and 45 are combined together to form an RS flip-flop (or a reset/set flip-flop) whose output serves as the aforementioned signal NFB, which is delivered to the switches 36 and 37 as well as the phase comparator 22.
The aforementioned triangular wave generating circuit has a phase-locked loop (PLL) configuration. The non-inverting input terminal of the comparator 41 receives voltage V1, which is expressed as follows:
      V    1    =            V      PX        a  
The non-inverting input terminal of the comparator 42 receives voltage V2, which is expressed as follows:
      V    2    =            V      MX        a  
In the above, reference symbols VPX and VMX designate the aforementioned voltages; and reference symbol ‘a’ designates a positive constant, which is expressed as follows:
  a  =                    R        82                              R          81                +                  R          82                      =                  R        84                              R          83                +                  R          84                    
Reference symbols R81, R82, R83, and R84 designate resistances of the aforementioned resistors 81, 82, 83, and 84 respectively.
In accordance with the aforementioned equations, a triangular wave output from the output terminal 46 has a maximal value VP and a minimal value VM, which correspond to the aforementioned voltages V1 and V2 respectively, so that a gain G is expressed as follows:
  G  =                              V          PX                -                  V          MX                                      V          P                -                  V          M                      =                                        V            PX                    -                      V            MX                                                              V              PX                        a                    -                                    V              MX                        a                              =      a      
Other types of triangular wave generating circuits not using PLL circuits have been conventionally developed, an example of which is disclosed in Japanese Patent Application Publication No. H01-318424. In this triangular wave generating circuit, rectangular waves having voltages +V and −V are alternately generated and are then subjected to integration using an integration circuit, thus producing a triangular wave. A closed-loop is constituted by directly connecting an integrator and an inverting amplifier between the output terminal and input terminal of the integration circuit. That is, the integration circuit integrates a triangular wave to generate an offset voltage, which is then negatively fed back to the input terminal of the integration circuit via the inverting amplifier, thus producing a triangular wave whose waveform is symmetrical with respect to the positive side and negative side.
The triangular wave generating circuit disclosed in Japanese Patent Application Publication No. 2004-7324 uses a PLL circuit, wherein it may be necessary for an engineer to design the circuitry to have a stable phase fixing ability. Improving the stability regarding the phase fixing operation may increase the circuit scale of the aforementioned loop filter. In addition, this may cause numerous jitters so that the output waveform of the class-D amplifier may have unwanted distortion.
The triangular wave generating circuit disclosed in Japanese Patent Application Publication No. H01-318424 does not use a PLL circuit, and therein it is possible to simplify the circuit configuration; however, due to the provision of a closed-loop, an engineer may experience difficulty in realizing stable operation. In addition, this circuit cannot follow up with variations of the voltages VPX and VMX; hence, when it is applied to a class-D amplifier not using a stabilized power source, there is a problem that the gain may become unstable.